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- Title
A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry.
- Authors
Wang, Chua-Chin; Hou, Zong-You; Wang, Deng-Shian; Hsieh, Chia-Lung
- Abstract
A single-ended six-transistor (6T) SRAM cell composed of a five-transistor (5T) cell and a read-assist low- V th PMOS as foot switch to prevent leakage damaging the data state is proposed in this work. Besides, a power–delay product (PDP) reduction circuitry design for nanoscale SRAMs is also proposed. The proposed PDP reduction circuitry design is composed of an adaptive voltage detection (AVD) circuit generating a boost-enable signal if the process variation is over a predefined range and a half-period word-line boosting (HWB) circuit responding to the enable signal. The proposed SRAM is implemented using TSMC 28-nm CMOS logic technology. PDP reduction is verified to be 41.73% according to the measurement results. The energy per access is 0.0206 pJ given the 800-mV power supply and 40-MHz system clock rate.
- Subjects
TAIWAN Semiconductor Manufacturing Co. Ltd.; STATIC random access memory; POWER resources
- Publication
Journal of Circuits, Systems & Computers, 2020, Vol 29, Issue 6, pN.PAG
- ISSN
0218-1266
- Publication type
Article
- DOI
10.1142/S0218126620500954