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- Title
Algorithm & Design of an Efficient Floating Point ADD/SUB Unit for an Experimental CPU.
- Authors
Joshi, A.; Lam, S. L.; Chan, Y. Y.
- Abstract
An 8-bit CPU is designed at gate level from scratch using custom chip approach. CPU has an 8-bit integer unit and 16-bit floating point unit. The instruction set includes shift, logic, integer and floating-point arithmetic instruction. The circuits are optimized by using more efficient algorithm. The algorithm discussed in this paper was applied for an 8-bit CPU design, however there is no reason that this couldn't be used for more powerful and serious CPU development. Currently no attempt has been made to include any special support or design for parallel MUL/ ADD / SUB operations[1][2]. An attempt has been made to improve conventional[6] algorithm. This paper discusses the design of FP ADD/SUB unit, with respect to algorithm and VHDL implementation, as all the functional units cannot be discussed in this paper.
- Subjects
CENTRAL processing units; VHDL (Computer hardware description language); COMPUTER hardware description languages; COMPUTER storage devices; DATA mining; DATABASE marketing; KNOWLEDGE management; INFORMATION resources management; ARTIFICIAL intelligence; ELECTRONIC data processing; INFORMATION science
- Publication
International Journal of Intelligent Information Technology Application, 2009, Vol 2, Issue 6, p273
- ISSN
1999-2459
- Publication type
Article