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- Title
Memory Efficient High Speed Systolic Array Architecture Design with Multiplexed Distributed Arithmetic for 2D DTCWT Computation on FPGA.
- Authors
Poornima, B.; Sumathi, A.; Prasanna Raj, P. Cyril
- Abstract
This paper presents customized Systolic Array Architecture (SAA) design of Dual Tree Complex Wavelet (DTCWT) sub band computation based on multiplexed Distributed Arithmetic Algorithm (DAA). The proposed architecture is memory efficient and operates at frequencies greater than 300 MHz in decomposing 256 x 256 input image. Three architectures such as reduced order structure, multiplexed DA structure and zero pad structure are designed and evaluated for its performances for DTCWT computation minimizing arithmetic operations with improved latency. The proposed design is modeled in Verilog HDL and is implemented on Spartan-6 and Virtex-5 FPGA considering Xilinx ISE FPGA design flow. The latency of proposed architectures is evaluated to be 15 clock cycles and throughput is estimated to be 4 outputs for every 5 clock cycles. The SAA architecture occupies less than 12% of FPGA resources and consumes less than 10 mW of power on FPGA platform.
- Subjects
SYSTOLIC array circuits; WAVELETS (Mathematics); HIGH-speed machining; ARITHMETICAL algebraic geometry; STIFF computation (Differential equations)
- Publication
Informacije MIDEM: Journal of Microelectronics, Electronic Components & Materials, 2019, Vol 49, Issue 3, p119
- ISSN
0352-9045
- Publication type
Article
- DOI
10.33180/InfMIDEM2019.301