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- Title
5.3 GHz 42% PAE class-E power amplifier with 532 mW/mm² power area density in 180 nm CMOS process.
- Authors
Alsuraisry, H.; Wu, M.-H.; Huang, P.-S.; Tsai, J.-H.; Huang, T.-W.
- Abstract
A 5.3 GHz high-efficiency and low-cost class-E power amplifier (PA) implemented in a 180 nm CMOS process is presented. Cascode configuration is utilised in the class-E PA to achieve high efficiency due to its high gain property and low drain-to-source parasitic capacitor. Through the trade-off between inductance and inductor loss, an optimised RF choke inductor for fully integrated class-E PA design can be selected to achieve high efficiency while maintaining compact circuit size. The class-E CMOS PA demonstrates the highest Power Added Efficiency (PAE) of 42% and greatest power area density of 532 mW/mm² in 0.263 mm² chip area to date.
- Subjects
GREAT Britain. Office of Communications; WHITE spaces (Telecommunication); TELEVISION; WORLD Radiocommunication Conference; INTERNATIONAL Telecommunication Union; BROADBAND communication systems
- Publication
Electronics Letters (Wiley-Blackwell), 2016, Vol 52, Issue 15, p1338
- ISSN
0013-5194
- Publication type
Article
- DOI
10.1049/el.2016.1629