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- Title
High speed modified carry save adder using a structure of multiplexers.
- Authors
Hameed, Ahmed Salah; Kathern, Manva Jawad
- Abstract
Adders are the hea1i of data path circuits for any processor in digital computer and signal processing systems. Growth in technology keeps suppo1ting efficient design of binary adders for high speed applications. In this paper, a fast and area-efficient modified carry save adder (CSA) is presented. A multiplexer based design of full adder is proposed to implement the structure of the CSA. The proposed design of full adder is employed in designing all stages of traditional CSA. By modifying the design of full adder in CSA, the complexity and area of the design can be reduced, resulting in reduced delay time. The VHDL implementations of CSA adders including (the proposed version, traditional CSA, and modified CSAs presented in literature) are simulated using Quartus II synthesis software tool with the altera FPGA EP2CST144C6 device (Cyclone II). Simulation results of 64-bit adder designs demonstrate the average improvement of 17.75%, 1.60%, and 8.81 % respectively for the worst case time, thermal power dissipation and number of FPGA logic elements.
- Subjects
DIGITAL signal processing; SOFTWARE development tools; SPEED
- Publication
International Journal of Electrical & Computer Engineering (2088-8708), 2021, Vol 11, Issue 2, p1591
- ISSN
2088-8708
- Publication type
Article
- DOI
10.11591/ijece.v11i2.pp1591-1598