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- Title
3.48-nW 58.4ppm/°C Sub-threshold CMOS Voltage Reference with Four Transistors and Two Resistors.
- Authors
Rasekhi, Mohammadreza; Ebrahimi, Emad; Aminzadeh, Hamed
- Abstract
In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1 V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18- μ m CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494 mV with temperature coefficient (TC) of 58.4 ppm/∘C across − 4 0 ∘ C to 85∘C; while the consuming power is lowered to 3.48 nW at the minimum supply of 0.8 V. The line sensitivity is 0.7%/V for the supply voltages from 0.8 V to 1.8 V, whereas the power supply ripple rejection (PSRR) is − 49.06 dB at 1 Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2 mV with σ / μ of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch.
- Subjects
VOLTAGE references; TRANSISTORS; JUNCTION transistors; BIPOLAR transistors; POWER resources; MONTE Carlo method; COMPLEMENTARY metal oxide semiconductors
- Publication
Journal of Circuits, Systems & Computers, 2022, Vol 31, Issue 7, p1
- ISSN
0218-1266
- Publication type
Article
- DOI
10.1142/S0218126622501195