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- Title
Fast Transient Capacitor-Less Low-Dropout Regulator Based on Output Voltage Spike Reduction Circuits for SOC Applications.
- Authors
Jahangiri, M.; Farrokhi, A.
- Abstract
A fast transient capacitor-less low-dropout regulator is presented in this study. The proposed LDO structure is based on Output Voltage Spike Reduction (OVSR) circuits and capacitance compensation circuits to enable a fast-transient response with ultra-low power dissipation and to make the LDO stable for a wide range of output load currents (0–50 mA). The slew rate is improved with more slew current from the OVSR circuit and unity gain bandwidth is improved by a capacitor multiplayer circuit. The proposed LDO has been simulated with a standard 0.18 μ m CMOS process. The output voltage of the LDO was set to 1.2 V for an input voltage of 1.4–2 V. The Simulation results verify that the transient times are less than 2.8 μ s and the maximum undershoot and overshoot are 20 mV while consuming only 26 μ A quiescent current. The proposed LDO is stable with an on-chip capacitor at the output node within the wide range of 1100 PF.
- Subjects
SYSTEMS on a chip; CAPACITORS; VOLTAGE spikes; CMOS integrated circuits; BANDWIDTHS
- Publication
Journal of Circuits, Systems & Computers, 2019, Vol 28, Issue 3, pN.PAG
- ISSN
0218-1266
- Publication type
Article
- DOI
10.1142/S0218126619500439