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- Title
A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test.
- Authors
Wei LIANG; Xingming SUN; Zhiqiang RUAN; Jing LONG; Chengtao WU
- Abstract
In Very Large Scale Integrated Circuits (VLSI) design, the existing Design-for-Test(DFT) based watermarking techniques usually insert watermark through re-ordering scan cells, which causes large resource overhead, low security and coverage rate of watermark detection. A novel scheme was proposed to watermark multiple scan chains in DFT for solving the problems. The proposed scheme adopts DFT scan test model of VLSI design, and uses a Linear Feedback Shift Register (LFSR) for pseudo random test vector generation. All of the test vectors are shifted in scan input for the construction of multiple scan chains with minimum correlation. Specific registers in multiple scan chains will be changed by the watermark circuit for watermarking the design. The watermark can be effectively detected without interference with normal function of the circuit, even after the chip is packaged. The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence Pc and higher coverage rate of watermark detection ΔS by comparing with the existing methods.
- Subjects
SEQUENTIAL circuits; DIGITAL image watermarking; LARGE scale integration of circuits; FOURIER transforms; FEEDBACK control systems; MATHEMATICAL models; VECTOR analysis
- Publication
Radioengineering, 2011, Vol 20, Issue 2, p533
- ISSN
1210-2512
- Publication type
Article