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- Title
Design and Analysis of a Symmetrical Low-κ Source-Side Spacer Multi-gate Nanowire Device.
- Authors
Gowthami, Y.; Balaji, B.; Rao, K. Srinivasa
- Abstract
In this paper, we propose a symmetrical low-κ source-side spacer multi-gate nanowire device design and analysis. High-κ spacer materials are currently researched extensively for improving electrostatic control and suppressing short-channel effects in nanoscale electronics. However, the excessive increase in fringe capacitance of high-κ spacers degrades the dynamic circuit performance. Surprisingly, this approach achieves a significant reduction in gate capacitance by maximizing the use of high-κ spacer material. Three different structures, a symmetrical dual-κ spacer, symmetrical low-κ drain-side spacer, and symmetrical low-κ source-side spacer multi-gate nanowire MOSFET, are simulated, and the symmetrical low-κ source-side spacer multi-gate nanowire device is found to achieve lower gate capacitance. Simulations performed in Silvaco TCAD showed drain current (Id) of 4.9 A/mm, OFF-current (Ioff) of 9.54 × 10−12 A, transconductance (gm) of 2.7 S/mm at Vgs = −0.4 V, cutoff frequency (fT) of 560 GHz, drain conductance (gd) of 0.657 S/mm, and ON-resistance (Ron) of 0.6 ohm mm The proposed structure is thus applicable for next-generation terahertz/millimeter wave high-power applications and thus is highly recommended for digital applications.
- Subjects
NANOELECTRONICS; NANOWIRE devices; MILLIMETER waves; NANOWIRES; METAL oxide semiconductor field-effect transistors; SILICON nanowires; ELECTRIC capacity
- Publication
Journal of Electronic Materials, 2023, Vol 52, Issue 4, p2561
- ISSN
0361-5235
- Publication type
Article
- DOI
10.1007/s11664-023-10217-z