We found a match
Your institution may have access to this item. Find your institution then sign in to continue.
- Title
DESIGN OF LOW POWER 2-D MULTIPLIER USING 2-D BYPASSING TECHNIQUE.
- Authors
Vinod Kumar D.; Krishnamacharya C.; Gangaraju B.; Uma Maheswara Rao K. V.; Avinash K.
- Abstract
Based on the simplification of the addition operations in a low-power bypassingbased multiplier, a low-cost low-power bypassingbased multiplier is proposed. Compared with rowbypassing multiplier, column-bypassing multiplier and 2-dimensional bypassing-based multiplier for 20 tested e×amples, the e×perimental results show that our proposed low-cost low power multiplier saves 15.1% of hardware cost and reduces 29.6% of the power dissipation on the average for 4×4, 8×8 and 16×16 multipliers.
- Subjects
ANALOG multipliers; LOW voltage integrated circuits; ENERGY dissipation
- Publication
International Journal on Intelligent Electronics Systems, 2013, Vol 7, Issue 2, p37
- ISSN
0973-9238
- Publication type
Article
- DOI
10.18000/ijies.30130