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- Title
SIMULATION OF CASCADED GATE-BASED TERNARY CONTENTADDRESSABLE MEMORY.
- Authors
S., PAVITHRA; DEEPA, P.
- Abstract
This paper presents a design for Gate-based ternary content-addressable memory (G-TCAM), utilizing G-AETCAM cells, which yields the location of given input information. The G-AETCAM cells utilizes flip-flop as memory component and control rationale hardware comprising of rationale entryways. One G-AETCAM cell encodes the input and put away the output into one encoded bit which brings about a match-line subsequent to passing from the input. G-AETCAM architecture is area efficient in terms of transistor count and speed of operations is high than the available TCAM architectures. The cascaded G-AETCAM cells are divided as banks, by considering each row as single bank of whole memory. The decoder logic used for memory design is modified by using reversible logic gate technique. Here, HL gate has been used instead of Line Decoder.
- Subjects
LOGIC circuits; ASSOCIATIVE storage; MEMORY
- Publication
I-Manager's Journal on Circuits & Systems, 2020, Vol 8, Issue 2, p29
- ISSN
2321-7502
- Publication type
Article
- DOI
10.26634/jcir.8.2.18087