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- Title
RELIABILITY CHARACTERIZATION OF A 3-μm CMOS/SOS PROCESS.
- Authors
Dugan, M. Patrick
- Abstract
A continuing study of advanced short-channel CMOS/SOS arrays has been carried out at the RCA Microelectronics Center (MEC) and at RCA Laboratories, Princeton, NJ, since 1981. A technique to assess the reliability of a new process relatively quickly consists of high-temperature accelerated stress testing of ICs by maintaining the temperature at 200°C, while biasing half the inputs at the positive supply voltage and half at ground. The results of these accelerated stress tests together with device analysis, were used to calculate a failure rate and to determine that time-dependent dielectric breakdown (TDDB) is the principal failure mechanism. No mechanism unique to the CMOS/SOS technology has been observed.
- Subjects
PRINCETON (N.J.); NEW Jersey; UNITED States; DIELECTRICS; MICROELECTRONICS; RELIABILITY in engineering; ENGINEERING; ELECTRONICS
- Publication
Quality & Reliability Engineering International, 1987, Vol 3, Issue 2, p99
- ISSN
0748-8017
- Publication type
Article
- DOI
10.1002/qre.4680030207