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- Title
A DfT Strategy for Guaranteeing ReRAM's Quality after Manufacturing.
- Authors
Copetti, T. S.; Fieback, M.; Gemmeke, T.; Hamdioui, S.; Poehls, L. M. Bolzani
- Abstract
Memristive devices have become promising candidates to complement the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are susceptible to manufacturing defects that may cause faulty behaviors not observed in CMOS technology, significantly increasing the challenge of testing these novel devices after manufacturing. This work proposes an optimized Design-for-Testability (DfT) strategy based on the introduction of a DfT circuitry that measures the current consumption of Resistive Random Access Memory (ReRAM) cells to detect not only traditional but also unique faults. The new DfT circuitry was validated using a case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library. The obtained results demonstrate the fault detection capability of the proposed strategy with respect to traditional and unique faults. In addition, this paper evaluates the impact related to the DfT circuitry's introduced overheads as well as the impact of process variation on the resolution of the proposed DfT circuitry.
- Subjects
NONVOLATILE random-access memory; MANUFACTURING defects; COMPLEMENTARY metal oxide semiconductors; MANUFACTURING processes; SCALABILITY
- Publication
Journal of Electronic Testing, 2024, Vol 40, Issue 2, p245
- ISSN
0923-8174
- Publication type
Article
- DOI
10.1007/s10836-024-06108-8